1. Field of the Invention
The present invention relates to a method for the detection and control of error propagation based on multilevel decision feedback equalization (MDFE), and to a memory device that makes use of this method.
More particularly, it relates to a method for controlling error propagation by means of the results of error propagation detection and error propagation offset detection involving the detection of the offset direction of a signal due to error propagation.
2. Description of the Related Art
FIG. 15 is a block diagram of the structure of a magnetic disk device that makes use of multilevel decision feedback equalization (MDFE), and of the signal processing system in particular. In FIG. 15, an input NRZ signal composed of 1 and 0 bit strings is converted by a (1-7) encoder into a (1-7) code having a code rule in which the maximum continuance of same-polarity codes is 8 and the number of continuous alternations is 1.
The output of the (1-7) encoder has a value of (plus/minus)1 sampled at a timing of 1/T. With respect to the output of the (1-7) encoder, (1/1-D)mod2 is computed by the write FF circuit 2, sent to the write/read head 3, and written to a disk.
In FIG. 15, the data written to the disk is read by a write/read head 3, and is amplified to a specific level through a head pre-amplifier circuit 4 and an AGC amplifier 5.
The output of the AGC amplifier 5 is inputted to a forward filter 6 of an MDFE circuit 10 and converted into a ternary signal (xe2x88x922, 0, +1). The output of a feedback filter 7 varies between input pulse polarity and reverse polarity. Specifically, the feedback filter 7 is assumed to be such that the polarity of the input reproduction signal pulses alternates.
Therefore, the output polarity of the feedback filter 7 is usually in the opposite direction from the polarity of the expected input to the forward filter 6. An addition circuit 8 finds the difference between the output of the forward filter 6 and the output of the feedback filter 7. As a result, the output of the addition circuit 8 has a waveform centered around a xe2x80x9c0xe2x80x9d level.
The output of the addition circuit 8 is then subjected to binary decision by a detector 9. The output of the detector 9 is a binary coded sequence, and is put in a quaternary state by 1-bit convolution by the MDFE circuit 10.
A (1-D)mod2 circuit 11 performs computation for write FF circuit 2 processing and inverse processing (1-D)mod 2, and decodes the (1-7) code by means of a (1-7) decoder 12. This results in the reproduction of the read signal.
Thus, the structure in decision feedback equalization is such that the decision results from the detector 9 are fed back to the input side through the feedback filter 7. This poses a problem in that an erroneous decision results in the propagation of the error.
One possible way to deal with this problem, as previously proposed by the inventors (PCT/98JP/05278), is to use a code conversion rule (d, k) to detect the occurrence of error propagation in decision feedback equalization, and make the slice level of a comparative decider 9 variable, so that error propagation is minimized.
FIGS. 16A and 16B are diagrams illustrating an example of when the polarity remains the same for nine or more continuous symbols. FIG. 16A is a write data string. In contrast, FIG. 16B is a signal string that has been read, and is a case in which the signal is missing at the 100th sample. When a signal is missing, the output of the detector 9 remains fixed at a constant level.
In the example in FIGS. 16A and 16B, the error propagates from the point of the missing signal at the 100th sample, and the output of the detector 9 continues fixed at the same polarity of xe2x88x921.
Meanwhile, FIGS. 17A and 17B are diagrams illustrating an example of continuous polarity alternations for two or more symbols. FIG. 17A is a write data string. In contrast, FIG. 17B is a signal string that has been read, and is a case in which the signal is missing at the 100th sample.
In the example in FIG. 17, the error propagates from the point of the missing signal at the 100th sample, and the output of the detector 9 is such that ten samples are fixed at +1 (interval I in FIG. 17B), and this is followed by a repeating cycle of polarity alternations of two or more continuous symbols (interval II in FIG. 17B).
The error in the read code strings illustrated in FIGS. 16 and 17 is a code pattern that violates the code conversion rule (d, k). The propagation of error caused by this d constraint violation and k constraint violation can be suppressed by the method disclosed in the previous application (PCT/98JP/05278).
However, further study by the inventors has revealed that error propagation which occurs when the code conversion rule is satisfied cannot be detected and suppressed by the method proposed in the above-mentioned previous application.
An example of this is illustrated in FIGS. 18A through 18C. FIG. 18A illustrates the comparative decider input of the detector (solid line) and the decider slice level (dotted line). FIG. 18B illustrates the direct current offset error level. FIG. 18C illustrates the AGC error signal level.
In this example, when there is no error propagation, the pattern is a continuous xe2x80x9c110000,xe2x80x9d but when error propagation occurs, it is found to be a continuous pattern of xe2x80x9c111001.xe2x80x9d
An object of the present invention is therefore to provide an error propagation detection method and apparatus for use in decision feedback equalization type detection, with which it is possible to detect error propagation even when a specific code conversion rule is satisfied in an MDFE system.
The constitution of the present invention for achieving the stated object involves multilevel decision feedback equalization in which the output of a comparative decider for deciding the level of an input signal is fed back to the input side through a feedback filter using a slice level as a reference, and the difference signal between the input signal and the feedback signal or a signal produced by inverting the feedback signal and adding it to the input signal is inputted to the comparative decider.
The present invention is characterized in that error propagation is detected from the input signal of the above-mentioned comparative decider and from the decision results of the comparative decider, the direction of the error propagation offset is detected from the decision results of the comparative decider, and as a result, the offset of the slice level of the comparative decider is controlled so as to be canceled out, or the DC level of the comparative decider input is controlled so as to cancel out the offset, which suppresses error propagation.
A first preferred aspect of the present invention is characterized in that, if we let the input signal of the above-mentioned comparative decider be y(k) and the output signal of said comparative decider be a binary signal a(k) expressed as xc2x11, then an error signal ev(k) expressed by ev(k)=[y(k)xe2x88x92Ideal y(k)]xc2x7sign[a(k)] is determined using a(kxe2x88x921)xe2x89xa0a(k+1) as an error computation condition, and the error signal ev(k) thus determined is checked to see whether it exceeds a specific value. If it is detected that the above-mentioned error signal ev(k) exceeds this specific value, the slice level of the above-mentioned comparative decider is controlled to a corresponding offset value.
A second preferred aspect of the present invention is characterized in that, in the first aspect, the above-mentioned error signal ev(k) is accumulated for a plurality of samples that satisfies the error computation condition a(kxe2x88x921)xe2x89xa0a(k+1), and if the cumulative value exceeds the above-mentioned specific value, the slice level of the above-mentioned comparative decider is controlled to a corresponding offset value.
A third preferred aspect of the present invention is characterized in that, in the first aspect, the above-mentioned error signal ev(k) is averaged for a plurality of samples that satisfies the error computation condition a(kxe2x88x921)xe2x89xa0a(k+1), and if the average value exceeds the above-mentioned specific value, the slice level of the above-mentioned comparative decider is controlled to a corresponding offset value.
A fourth preferred aspect of the present invention is characterized in that, if we let the input signal of the above-mentioned comparative decider be y(k) and the output signal of said comparative decider be a binary signal a(k) expressed as xc2x11, then an oscillation error signal is computed using a(kxe2x88x921)xe2x89xa0a(k+1) as an oscillation error computation condition, and the oscillation error signal thus computed is checked to see whether it exceeds a specific value. If it is detected that the above-mentioned oscillation error signal exceeds this specific value, the slice level of the above-mentioned comparative decider is controlled to a corresponding offset value.
A fifth preferred aspect of the present invention is characterized in that, in the above-mentioned fourth aspect, the above-mentioned oscillation error signal computed using the above-mentioned oscillation error computation condition is accumulated for a plurality of samples, and if the cumulative value exceeds a specific comparison reference value, the slice level of the above-mentioned comparative decider is controlled to a corresponding offset value.
A sixth preferred aspect of the present invention is characterized in that, in the above-mentioned fourth aspect, the above-mentioned oscillation error signal computed using the above-mentioned oscillation error computation condition is averaged for a plurality of samples, and if the average value exceeds a specific comparison reference value, the slice level of the above-mentioned comparative decider is controlled to a corresponding offset value.
A seventh preferred aspect of the present invention is characterized in that, in the above-mentioned first or fourth aspect, a +1 or xe2x88x921 majority decision is made for the output bits from the above-mentioned comparative decider, and the offset direction of the above-mentioned input signal is decided from the results of the above-mentioned majority decision. The slice level of the above-mentioned comparative decider is controlled to a corresponding offset value in the opposition direction from the above-mentioned decided offset direction.
An eighth preferred aspect of the present invention is characterized in that, in the above-mentioned first or fourth aspect, a +1 or xe2x88x921 majority decision is made for one cycle of output bits from the above-mentioned comparative decider, and the offset direction of the above-mentioned input signal is decided from the results of the above-mentioned majority decision. The slice level of the above-mentioned comparative-decider is controlled to a corresponding offset value in the opposition direction from the above-mentioned decided offset direction.
A ninth preferred aspect of the present invention is characterized in that the squared difference or the difference between the above-mentioned input signal and an ideal signal inferred from the decision results of the comparative decider is determined, these squared difference signals or difference signals are accumulated between a plurality of samples, and a cumulative squared difference signal or cumulative difference signal is determined. The above-mentioned cumulative squared difference signal or cumulative difference signal is checked to see whether it exceeds a specific value, and if it is detected that the cumulative squared difference signal or cumulative difference signal exceeds this specific value, slice level of the above-mentioned comparative decider is controlled to a corresponding offset value.
A tenth preferred aspect of the present invention is characterized in that the squared difference or the difference between the above-mentioned input signal and an ideal signal inferred from the decision results of the comparative decider is determined, and a signal is determined for which the polarity of the decision results of the above-mentioned comparative decider has been crossed with the above-mentioned squared difference or difference signal. These signals for which the polarity has been crossed with the above-mentioned squared difference or difference signal are then accumulated over a specific sample interval, and if the absolute value of the above-mentioned accumulated values exceeds a specific value, the slice level of the above-mentioned comparative decider is controlled to a corresponding offset value.
Further characteristics of the present invention will become clear from the embodiments of the present invention which are described through reference to the figures below.